Urban sprawl has been a continued problem in many rural communities, including Huntingdon County, Pennsylvania. This is why, every year, they choose to legally protect select agricultural lands to curb the effects of growing urban populations, namely from the Northeast part of the county near State College. We have been asked by the Huntingdon County Conservation District to rank the lands that have applied to be protected in order to determine which ones will be chosen. There is a specific set of criteria that we are given, and each land is given a score. The criterion is based on how likely a parcel is to be developed by contractors or businesses etc. Examples of criteria include; a property's road frontage, distance from developments or businesses, distances from other farmlands, and the percentage of land used for agricultural purposes. Using ArcGIS, we mapped out each of the farmlands and determined their potential for development as well as agricultural use. These lands were then given a score, ranked from highest to lowest, and given to the Huntingdon County Conservation District for them to choose which parcels they should preserve.  

The steady progress of computing power, as predicted by Moore's Law, has stagnated in recent years, leading the industry to focus on parallelism as the primary means of driving performance improvements. While parallel computing offers significant potential, it also introduces challenges related to non-deterministic behavior, especially in object-oriented programming languages like Java.

To address these challenges, researchers have developed Deterministic Parallel Java (DPJ), an extension to the Java programming language that enforces deterministic parallelism by default. However, current implementations of DPJ are primarily software-based, relying on the underlying hardware to provide the necessary performance and efficiency.

In this research project, I aim to explore the potential of implementing the DPJ approach in hardware, specifically on a Field Programmable Gate Array (FPGA) platform. By mapping the DPJ concepts directly onto reconfigurable hardware, I seek to achieve significant performance and energy efficiency gains, as well as investigate the hardware-software co-design opportunities that this approach offers.

The primary goals of this research are to (1) design and implement the first FPGA-based architecture for DPJ, and (2) contribute to the broader body of knowledge in the field of computer architecture. Additionally, this project provides a valuable opportunity for me to gain hands-on experience with graduate-level research and to represent the hardware aspects of computer science at the Liberal Arts Symposium.